(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method of forming thin salicide (self-aligned metal silicide), on elements of a P channel metal oxide semiconductor (PMOS), device, while simultaneously forming thicker salicide on elements of an N channel metal oxide semiconductor (NMOS), device.
(2) Description of Prior Art
The emergence of micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, have allowed the performance of semiconductor devices to be increased while the processing costs for these same devices have been reduced. Sub-micron features allow performance degrading junction capacitances to be reduced, in addition the greater amount of smaller semiconductor chips realized from a specific size semiconductor wafer, still providing device densities equal to or greater than larger counterpart chips, have allowed the processing costs for a specific semiconductor chip to be reduced. However specific aspects of micro-miniaturization can present fabrication situations which have to be addressed. For example the narrower channel regions now available with micro-miniaturization result in word line widths of 0.20 xcexcm or less. To avoid low word line resistance, in addition to avoiding metal silicide agglomeration, thick metal silicide regions are formed on the word lines, with the self-aligned metal silicide (salicide), procedure, simultaneously forming metal silicide on exposed source/drain regions. However when employing a salicide procedure for complimentary metal oxide semiconductor (CMOS), devices, the thicker metal silicide desired for the low word line resistance for the NMOS component of the CMOS device, can adversely influence the yield of the PMOS component, when the same metal silicide layer is formed on the PMOS source/drain region. The thicker metal silicide layer can induce junction leakage at the P+/N well interface of the PMOS component.
The present invention will teach a process for simultaneously forming a thick metal silicide layer on elements of an NMOS device, while the same salicide procedure results in a thinner metal silicide layer on the word line and source/drain regions of the PMOS component of a CMOS device. This is accomplished via incorporation of specific elements into the PMOS components prior to the salicide procedure, with the specific elements used to retard metal silicide formation. Prior art, such as Guo, in U.S. Pat. No. 6,323,077 B1, Wieczorek et al, in U.S. Pat. No. 6,150,243, Nistler, in U.S. Pat. No. 6,072,222, and Wieczorek et al, in U.S. Pat. No. 6,255,214, describe methods of forming metal silicide layers on regions of a semiconductor device. None of the above prior art however describe the novel process sequence employed in the present invention wherein a single salicide procedure is used to form a metal silicide layer on components of a PMOS device, thinner than the metal silicide layer simultaneously formed on elements of an NMOS device.
It is an object of this invention to simultaneously form metal silicide on the word line and source/drain regions of both NMOS and PMOS devices.
It is another object of this invention to simultaneously form metal silicide on both PMOS and NMOS regions, with the metal silicide on PMOS elements thinner than the metal silicide formed on the NMOS elements.
It is still another object of this invention to implant specific elements such as titanium (Ti), tantalum (Ta), vanadium (V), and rhenium (Re), during the PMOS source/drain implantation procedure, with these specific elements retarding the subsequent salicide formation on PMOS elements, allowing a thinner metal silicide to be formed on the PMOS elements when compared to metal silicide simultaneously formed on counterpart NMOS elements.
In accordance with the present invention a method of forming thinner metal silicide on elements of a PMOS device, while simultaneously forming thicker metal silicide on elements of a NMOS device, is described. After formation of an N well region in an area of a semiconductor substrate to be used for PMOS device fabrication, a gate insulator layer and gate structures, comprised with insulator sidewall spacers, are defined on areas of the semiconductor substrate to be used for both PMOS and for NMOS fabrication. After formation of a heavily doped source/drain region in the NMOS region, a photoresist blockout shape is to allow P type ions, as well as specific metal ions, to be implanted only into regions of the PMOS device to be used as subsequent heavily doped source/drain regions. Deposition of a metal layer is followed by an anneal procedure resulting in metal silicide formation on exposed silicon and polysilicon regions of both PMOS and NMOS elements. The presence of the specific metal ions in the PMOS word line and source/drain region retarded the formation of metal silicide in these regions resulting in a thinner metal silicide layer in PMOS regions than the thicker, or non-retarded metal silicide simultaneously formed in NMOS regions. Regions of unreacted metal, located on the insulator sidewall spacers, are selectively removed.